1. Field of the Invention
The present invention relates to a non-volatile electrically erasable and, programmable semiconductor memory device, and more particularly, to a non-volatile semiconductor memory device including a defect-check circuit.
2. Description of the Related Art
Semiconductor memory devices can be classified into two groups, volatile semiconductor memory devices and non-volatile semiconductor memory devices. The volatile semiconductor memory devices include dynamic random access memories and static random access memories. The volatile semiconductor memory devices have high speed in read and write modes. However, volatile semiconductor memory devices need a constant external electric power source to store data in a memory cell.
The non-volatile semiconductor memory devices include mask read only memories (MROM), programmable read only memories (PROM), erasable and programmable read only memories (EPROM), and electrically erasable programmable read only memories (EEPROM). Unlike volatile semiconductor memory devices, non-volatile semiconductor memory devices store data in memory cells permanently. However, a user cannot freely write and read (or program) with an electronic system including an MROM, PROM or EPROM. Therefore, a need exists for highly integrated, high performance EEPROM implemented in supplementary memory devices or system-program storage devices that continuously refresh data.
To increase the integration of EEPROM, the area occupied by memory cells in the EEPROM needs to be reduced. A proposed EEPROM includes memory cells of NAND structure wherein the number of contact holes between bit-lines and the number of select transistors per cell can be reduced. Such a NAND structure cell is disclosed on pages 412 to 415 of IEDM published in 1988, under the title of xe2x80x9cNEW DEVICE TECHNOLOGIES FOR 5V-ONLY 4Mb EEPROM WITH NAND STRUCTURE CELLxe2x80x9d. The proposed NAND structure includes a first select transistor including a drain connected to a corresponding bit line via a contact hole, a second select transistor including source connected to a common source line, and a cell string or NAND cell unit, formed of eight memory transistor channels in series connected between the source of the first select transistor and the drain of the second select transistor. The proposed NAND cell string is formed on a substrate of P type semiconductor material. Each memory transistor includes a floating gate on a gate oxide film in a channel region between the source and drain regions, and a control gate formed on the floating gate through an interlayer insulating layer.
To program a memory transistor selected in a cell string, all memories of transistors in the cell string are erased simultaneously prior to programming. Simultaneous erasing of all the memories, or flash erasing, can be performed by supplying 0 Volt to the bit-line and 17 Volt to a gate of the first select transistor and control gates of all the memory transistors. That is, all the memory transistors become transistors of enhancement mode and those are assumed to be transistors programmed by xe2x80x9c1xe2x80x9d as a binary digit.
To program the selected memory transistor with a binary digit xe2x80x9c0xe2x80x9d, a power of 22 Volts is applied to gates of the first transistor and the bit-line, and a control gate of each of the memory transistors positioned between the first transistors and the selected memory transistors. A power of 0 Volt is applied to a control gate of the selected memory transistor,a gate of the second select transistor and a gate of each of the memory transistors positioned between the selected memory transistor and the source lines. Therefore, the selected memory transistor is programmed according to Fowler-Nordheim tunneling (F-N tunneling) through hole from drain to floating gate.
However, in such a programming method, because a high voltage is applied to the drain of the selected memory transistor, the gate oxide film is stressed, thereby causing leakage current from the thin gate oxide film. Accordingly, the ability to retain data of the memory cell is lowered as a function of the frequency of erasing and programming, thereby reducing the reliability of the EEPROM.
To solve such a problem, there has been proposed an improved device in which NAND cell units are formed at P-type well regions on a N-type semiconductor substrate and an improved erasing and programming technique using the same, on pages 129-130 of xe2x80x9cSymposium on VLSI Technologyxe2x80x9d issued in 1990, under the title of xe2x80x9cA NAND STRUCTURED CELL WITH A NEW PROGRAMMING TECHNOLOGY FOR HIGHLY RELIABLE 5V-ONLY FLASH EEPROMxe2x80x9d. The erasing operation of memory cells in the NAND unit is performed by applying 0V to all of the control gates and a high voltage of 20V to P type well regions and N type substrate. The electronics are uniformly discharged from floating gates of all memory transistors to P-type wells. As a result, the threshold voltage of each of the memory transistors becomes a negative voltage of approximately xe2x88x924V and the transistor goes to a state of depletion mode by which binary logic xe2x80x9c0xe2x80x9d is stored.
To program the selected memory transistor in the NAND cell unit, 20V is applied to a gate of the first select transistor and a control gate of the selected memory transistor, 0V is applied to a gate of the second select transistor, and a middle voltage of 7V is applied to a control gate of each of the non-selected memory transistors.
If the selected memory transistor is written or programmed by a binary logic xe2x80x9c1xe2x80x9d, 0V is applied to bit-lines connected to the NAND cell unit and electronics are implanted onto a floating gate of the selected memory transistor, thereby the transistor is changed into an enhancement mode. In contrast, if the selected memory transistor is programmed by a binary logic xe2x80x9c0xe2x80x9d, a middle voltage of 7V that corresponds to a program preventing voltage is applied to the corresponding bit-lines, thereby preventing the programming operation in the selected memory transistor. Such a programming operation allows electronics to be uniformly implanted into the floating gate through a gate oxide from the P type-well, thereby the thin gate oxide film is not stressed, and current leakage in a gate oxide film is prevented.
As described above, since the NAND type of flash EEPROM, including flash erasing which has appeared as EEPROM design technique has been improved, has a higher integration than a NOR type or an AND type of EEPROM, it is preferably applied to large scale supplementary memory devices.
In NAND type lash memory, a memory cell array includes a plurality of cell array blocks including a plurality of cell strings, a plurality of word lines (W/L) arranged in a first direction, for example, in a transverse direction, to select memory cell transistors. The select memory cell transistors include floating gates in the cell strings, and a plurality of bit lines (B/L) arranged in a direction opposite to the first direction, for example, in a longitudinal direction. The W/Ls are electrically connected to control gates of the memory cell transistors. The W/L itself made in a fabricating process plays a role of the control gate. One W/L may be electrically connected to another W/L adjacent to the W/L. Such phenomenon, hereinafter, referred to as W/L short, can result from deposition process, photolithography process, defect in etching process, or defect in design. When such W/L short is created in a chip, it can be difficult for a specific memory cell transistor selected to perform an access operation, that is, reading, writing or programming, or erasing.
A cell memory array of the NAND type flash memory includes a plurality of block units. One block may include a plurality of memory cell transistors, for example, memory cell transistors of 4 k byte. Where a W/L short is created in a memory cell in a block, a test during manufacture needs a defect test technique by which such defect can be checked. After sending out products for a small storage capacity less than a practical storage capacity, an access preventing technique is needed to prevent a user from access to a defected block in the memory. Whether a W/L short is created can be determined in a memory block in a test mode of wafer level or package level. Where the W/L short is checked, a technique is needed wherein the corresponding memory blocks are treated as bad blocks.
Therefore, a need exists for a system and method for a word line defect check implemented in a non-volatile semiconductor memory device.
Accordingly, it is an object of the present invention to provide a no-volatile semiconductor memory device wherein defects in word lines can be determined.
It is another object of the present invention to provide a semiconductor memory device including a word line defect check circuit that can check defects in word lines and treat the corresponding memory block as bad blocks when defects in word lines are created in a random memory block.
It is yet another object of the present invention to provide a method wherein a word line short is detected in a test mode of package level and an access to a memory block including a word line short can be prevented.
It is still another object of the present invention to provide a non-volatile semiconductor memory device including a performance by which preventing an access to a block can be released if needed although the access to the block including defect of a word line short is prevented.
It is further another object of the present invention to a NAND flash non-volatile semiconductor memory device that can easily check a defected memory block and release a prevention of access or a prevented access.
To achieve the objects, according to an embodiment of the present invention, a non-volatile semiconductor memory device is provided including a memory cell array including a plurality of cell array blocks. Each cell array block includes a plurality of cell strings that include floating gate memory cell transistors wherein drain-source channels are in series connected each other between string select transistors and ground select transistors and that its control gates are correspondingly connected to a plurality of word lines. The non-volatile semiconductor memory device includes a word line short check circuit that applies voltages of different levels to each of the plurality of word lines that is adjacent from one another during a predetermined charging time, and that generates a short detect signal that indicates whether short between adjacent word lines is occurred, by checking voltage levels of the word lines that were supplied with a same level of voltage, after the charging time is lapsed by a predetermined time.
The word line short check circuit preferably includes a bias part for supplying the even word lines of the plurality of word lines with a first voltage and the odd word lines with a second voltage lower than the first voltage during the predetermined charging time, and a sense part for checking voltage, levels of the even word lines to generate a short sense signal after the charging time is lapsed by a predetermined time to check whether short between the odd word lines and the even word lines is created or not.
According to an embodiment of the present invention, a method of testing a short defect between word lines of a non-volatile semiconductor memory device is provided. The non-volatile semiconductor memory device includes a memory cell array including a plurality of cell array blocks. Each cell array block includes a plurality of cell strings including floating gate memory cell transistors wherein its drain-source channels are in series connected each other between string select transistors and ground select transistors and that its control gates are correspondingly connected to a plurality of word lines. The method includes applying different levels of voltage to adjacent word lines out of the plurality of word lines during the predetermined charging time, and checking voltage levels of the word lines that were applied with same levels of voltage among the plurality of word lines after the charging time is lapsed by a predetermined time. The method further includes analyzing the result of checking to generate a short sense signal that indicates whether short between the adjacent word lines is created, and preventing by a block unit cell array blocks from being accessed in a normal operation when the short sense signal is at a state level that word line short is created in the cell array blocks.